In class-D audio amplifiers, for various reasons, such as diagnostics of the state of speakers or else for applying thereto linearization techniques, there frequently arises the need to read accurately the current that the final stage supplies to the load.
Since it is not generally convenient to resort to costly and cumbersome external circuits for current sensing, recourse is had to internal sensing, by measuring the current supplied by power MOSFETs. At low frequency these currents are equal to the load current in so far as the current that flows in filter capacitors is negligible.
In this connection, FIG. 1 illustrates a full-H bridge 11 of a final stage of a power audio amplification circuit. The architecture of the final stage of a class-D amplification circuit is in itself known to the person skilled in the sector, and in general comprises a comparator, which compares the input signal with a signal produced by a triangular-wave generator for supplying a PWM driving signal to a switching controller, which in turn controls the states of opening and closing of the MOSFETs of the H bridge 11, to the gate electrodes of which it supplies the PWM driving signal. The H bridge 11 is a full bridge, which comprises two half-bridges: a first half-bridge 12, which comprises a high-side power MOSFET 13a, i.e., one connected to the supply VDD, and a low-side power MOSFET 13b, i.e., one connected to ground GND, which supply, to a first output node OUTP that is common between the drain electrode of the low-side transistor and the source electrode of the high-side transistor, a first output current IOUT; and a second half-bridge 22, which comprises a respective high-side MOSFET 23a and a respective low-side MOSFET 23b that supply to a second output node OUTM a second current IOUTM.
The output current IOUTP, IOUTM of each half-bridge 12, 22 of the bridge 11 is supplied, through a corresponding LC filter 14, 24, the function of which is also in itself known to the person skilled in the sector of class-D audio amplifiers and is not described any further herein, to the input terminals of a speaker 15, on which it determines a load current ILOAD. It should be noted that in FIG. 1 the high-side transistors are of an n-channel type, but they may also be of a p-channel type, in which case the output current is detected on the drain electrode.
The solution currently adopted for carrying out reading of the load current ILOAD is represented with reference to the circuit diagram of FIG. 2 and to the corresponding time plot of FIG. 3.
It envisages sampling a drain-to-source voltage VDSLP of the low-side transistor 13b (or 23b) of the circuit of FIG. 1 at the instant, designated by ts in FIG. 3, in which the current ripple due to the finite inductance of the external LC filter 14 (or 24) vanishes.
This is obtained via a sensing circuit 30, which comprises a pre-amplifier 31 for carrying out reading of the drain-to-source voltage VDSLP of the low-side transistor 13b, the pre-amplifier 31 being connected with its two input pins to the drain and to the source of the low-side transistor 13b via driven protection switches 32 inserted on each connection between the drain and source and the respective pins of the preamplifier 31. These switches 32 are driven by a protection signal, SWPRP, so as to protect the preamplifier 31 from high voltage, whilst further sampling switches set on the outputs of the preamplifier 31 constitute, together with respective sampling capacitors, connected to the analog ground AGND, a sample and hold circuit 33, driven by a corresponding sample and hold signal SWSH, which drives the states of opening and closing of the switches of the circuit 33, for an analog-to-digital converter (ADC) 34.
In this regard, FIG. 3 illustrates plots representing as a function of time t the first output current IOUTP, the drain-to-source voltage VDSLP, the protection signal SWPRP, and the sample and hold driving signal SWSH. As may be noted, the drain-to-source voltage VDSLP is sampled at a sampling instant ts, where, at d.c. and at low frequencies, it is proportional to the load current ILOAD through the switch-on resistance RDSONLP of the low-side transistor 13b. 
Moreover, designated by ta in FIG. 3 is the instant of turning-off of the high-side MOSFET, for example 13a, and turning-on of the low-side MOSFET, for example 13b. Designated by tb is the instant of turning-off of the low-side transistor and turning-on of the high-side transistor.
Once the drain-to-source voltage VDSLP has been sampled, the information on current is obtained from the comparison with a reference drain-to-source voltage VDSREF. This reference drain-to-source voltage VDSREF is generated by a reference power MOSFET 13c (illustrated in FIG. 4), electrically and thermally coupled to the MOSFET 13b that delivers the first output current IOUTP, with known aspect ratio and current.
By computing the ratio between the drain-to-source voltage VDSLP and the reference drain-to-source voltage VDSREF, the first output current IOUTP is obtained, as shown in FIG. 4, where designated by IREF is the current of a reference-current generator 16, which forces the current into the drain of the MOSFET 13c. The drain-to-source switch-on resistances the MOSFETs 13b and 13c are designated as RDSONLP and RDSREF. The output current IOUTP can thus be computed according to these quantities as follows:VDSREF=RDSREF·IREF VDSLP=RDSONLP·(−IOUTP)IOUTP=−(IREF·RDSREF/RDSONLP)·VDSLP/VDSREF 
The drain-to-source voltages VDSLP and VDSREF are measured through the sensing circuit 30 of FIG. 2, whereas the other parameters are known design parameters or are obtained following upon a further trimming operation.
The circuit just described with reference to FIGS. 2 and 3 presents various limitations.
As shown in the plot of FIG. 5, which represents the output current IOUTP and a corresponding current ISAMP sampled by the circuit 30, an error on the sampling instant ts causes in fact a reading error. Ideally, sampling of the drain-to-source voltage VDSLP must be carried out when the effect of the ripple in the inductance of the LC filter 14 is zero and the output current IOUTP is equal to the mean value of the load current ILOAD. If sampling is not made at this instant, but after a time Δt, superimposed on the signal is an undesirable current contribution ΔI due to the ripple current, as emerges from FIG. 5, represented in which are the current ILOAD and two values of current IIDEAL and ISAMP, one evaluated at the ideal sampling time tIDEAL and the other at the effective sampling time tSAMP=tIDEAL+Δt.
Sampling is moreover limited by saturation of the final stage.
When the signal grows, the duty cycle of the low-side transistor decreases (this time interval is represented by the high level of the protection signal SWPRP in FIG. 3). When the duty cycle becomes comparable to or shorter than the time of charging of the gate, plus the settling time both of the reading circuit and of the sample and hold circuit, it is no longer possible to make an accurate reading of the current. With reference to FIG. 3, this means that the time interval in which the sample and hold signal SWSH is high is too short. To prevent this problem linked to saturation, beyond a certain level of signal it would be possible to choose to switch the reading of current on the other half-bridge, but switching of reading to the other half-bridge entails the high risk of incurring in discontinuities.